1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a layout of a plurality of circuit blocks formed on a semiconductor substrate.
2. Description of Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) often includes a redundant circuit for saving a defective address in the device. As described in Japanese Patent Application Laid-open No. 2001-43695, the redundant circuit includes a fuse element that stores therein a defective address, a comparing circuit that compares an address stored in the fuse element with an address for which an access is requested, and a determining circuit that determines whether all bits of the address for which the access is requested match those of the defective address stored in the fuse element. When the determination result shows a match of all the bits, an alternative access is performed to a redundant word line or a redundant bit line instead of a defective word line or a defective bit line. With this method, an address assigned to the defective word line or the defective bit line is saved, so that the device is handled as a good chip.
As a well-known layout of a redundant circuit, there is a layout described in Japanese Patent Application Laid-open No. 2006-237642. In the patent document, as shown in FIG. 1 thereof, there is disclosed a layout in which a plurality of fuse elements are arranged in one direction and a plurality of comparing circuits corresponding to the fuse elements are arranged close to the fuse elements, respectively, in the same direction. A pitch of the comparing circuit array is set to be smaller than a pitch of the fuse element array, thus providing a space in the comparing circuit array, in which a common signal line required for a plurality of comparing circuits is arranged.
The application of the fuse elements is not limited to semiconductor memory devices, and the fuse elements are used in general semiconductor products such as a CPU (Central Processing Unit), an MCU (Micro Control Unit), a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), and an ASSP (Application Specific Standard Circuit). These products include a large number of fuse elements and processing circuits for processing signals from the fuse elements, which are compactly arranged in a predetermined area on a semiconductor substrate. A variety of systems are applied to the fuse elements, such as a technique of blowing a wiring with an optical laser, a technique of melting down a wiring with an electric fuse, and a technique of breaking down a gate insulating layer of a transistor or a PN junction with an antifuse.
However, because the layout described in Japanese Patent Application Laid-open No. 2006-237642 is for simply laying out wirings in a space obtained in a comparing circuit array, a determining circuit that collects a plurality of comparison result signals output from a plurality of comparing circuits respectively corresponding to fuse elements and generates a determination result signal indicating whether it is redundant or not should be laid out in a separate area. Because one determining circuit is required for a plurality of comparing circuits, in the layout described in Japanese Patent Application Laid-open No. 2006-237642, a plurality of determining circuits are arranged in a scattered manner along the direction of arranging the comparing circuits. As a result, the shape of the layout of the redundant circuit becomes an irregular shape that is wasteful, resulting in a problem of increasing a chip area.
The problems explained above are not limited to a redundant circuit of a semiconductor memory device, but are problems that usually occur in a semiconductor device that includes a plurality of circuit blocks formed on a semiconductor substrate in which each of the circuit blocks includes a plurality of unit circuits, a plurality of processing circuits each being allocated to each of the unit circuits, and a common circuit that is commonly allocated to a plurality of processing circuits.